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atmel-8855f-dts-AT30TS750A-datasheet_102014 features ? single 1.7v to 5.5v supply ? measures temperature from -55 ? c to +125 ? c ? highly accurate temperature measurements requiring no external components ? 0.5c accuracy (typical) over the 0 ? c to +85 ? c range ? 1.0c accuracy (typical) over the -25 ? c to +105 ? c range ? 2.0c accuracy (typical) over the -40 ? c to +125 ? c range ? user-configurable resolution ? 9 to 12 bits (0.5 ? c to 0.0625 ? c) ? user-configurable high and low temperature limits ? nonvolatile registers to retain user-configured or pre-defined power-up defaults ? register locking to prevent erroneous misconfiguration ? register lockdown for permanent, non-changeable device configuration ? alert output pin for indicating temperature alarms ? 2-wire i 2 c and smbus ? compatible serial interface ? supports smbus timeout ? supports smbus alert and alert response address (ara) ? selectable addressing allows up to eight devices on the same bus ? built-in noise suppression filtering for clock and data input signals ? low power dissipation ? 75 a active current (typical) during temperature measurements ? shutdown mode to minimize power consumption ? 1 a shutdown current (typical) ? one-shot mode for single temperature measurement while in shutdown mode ? pin and software compatible to industry-standard lm75-type devices ? industry standard green (pb/halide-free/rohs compliant) package options ? 8-lead soic (150-mil) ? 8-lead msop (3.0 x 3.0mm) ? 8-pad ultra thin dfn (udfn ? 2.0 x 3.0 x 0.6mm) AT30TS750A 9- to 12-bit selectable, 0.5c accurate digital temperature sensor with nonvolatile registers datasheet
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 2 table of contents 1. description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2. pin descriptions and pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4. device communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.2 stop condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.3 acknowledge (ack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4.4 no-acknowledge (nack) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5. device operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.1 temperature measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.2 temperature alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2.1 fault tolerance limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.2.2 comparator mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5.2.3 interrupt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.3 shutdown mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.3.1 one-shot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6. registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.1 pointer register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.2 temperature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.3 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.3.1 os bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.2 r1:r0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.3.3 ft1:ft0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.4 pol bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.5 cmp/int bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.6 sd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.3.7 nvrbsy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.4 nonvolatile configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.4.1 nvr1: nvr0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.4.2 nvft1:nvft0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4.3 nvpol bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4.4 nvcmp/int bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4.5 nvsd bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4.6 rlckdwn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4.7 rlck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5 t low and t high limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.6 nonvolatile t low and t high limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7. register locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 8. operations allowed during nonvolatile busy status . . . . . . . . . . . . . . . 31 9. other commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 9.1 copy nonvolatile registers to volatile registers . . . . . . . . . . . . . . . . . . . . . . 32 9.2 copy volatile registers to nonvolatile registers . . . . . . . . . . . . . . . . . . . . . . 33
3 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 10. smbus features and i 2 c general call . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.1 smbus alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.2 smbus timeout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 10.3 general call . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 11. electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.2 dc and ac operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 11.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 11.4 temperature sensor accuracy and conversion characteristics . . . . . . . . . . 38 11.5 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 11.6 nonvolatile register characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.7 power-up conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 11.8 pin capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 11.9 input test waveforms and measurement levels . . . . . . . . . . . . . . . . . . . . . . 40 11.10 output test load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 12. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.1 atmel ordering code detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 12.2 green package options (pb/halide-free/rohs compliant) . . . . . . . . . . . . . . 41 13. part marking detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 14. packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14.1 8s1 ? 8-lead jedec soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 14.2 8xm ? 8-lead msop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 14.3 8ma2 ? 8-pad udfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 15. errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 15.1 no errata. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 16. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 4 1. description the atmel ? AT30TS750A is a complete, precise temperature monitoring device designed for use in a variety of applications that require the measuring of local temperatures as an integral part of the system's function and/or reliability. the AT30TS750A device combines a high-precision digital temperature sensor, programmable high and low temperature alarms, and a 2-wire i 2 c and smbus (system management bus) compatible serial interface into a single, compact package. the temperature sensor can measure temperatures over the full -55c to +125c temperature range and has a typical accuracy as precise as 0.5c from 0c to +85c. the result of the digitized temperature measurements are stored in one of the AT30TS750A's internal registers, which is readable at any time through the device's serial interface. the AT30TS750A utilizes flexible, user-programmable internal registers to configure the temperature sensor's performance and response to high and low temperature conditions. the device also contains a set of nonvolatile registers to retain the configuration and temperature limit settings even after the device has been power cycled, thereby eliminating the need for the device to be reconfigured after each power-up operation. this additional flexibility permits the device to run self-contained and not rely upon a host controller for device configuration. a dedicated alarm output activates if the temperature measurement exceeds the user-defined temperature and fault count limits. to reduce current consumption and save power, the AT30TS750A features a shutdown mode that turns off all internal circuitry except for the internal power-on reset (por) and serial interface circuits. the device can also be configured to power-up in the shutdown mode to ensure that the device remains in a low-power state until the user wishes to perform temperature measurements. the AT30TS750A is factory-calibrated and requires no external components to measure temperature. with it?s flexibility and high-degree of accuracy, the AT30TS750A is ideal for extended temperature measurements in a wide variety of communication, computer, consumer, environmental, industrial, and instrumentation applications.
5 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 2. pin descriptions and pinouts table 1. pin description symbol name and function asserted state type scl serial clock: this pin is used to provide a clock to the device and is used to control the flow of data to and from the device. command and input data present on the sda pin is always latched in on the rising edge of scl, while output data on the sda pin is always clocked out on the falling edge of scl. the scl pin must either be forced high when the serial bus is idle or pulled-high using an external pull-up resistor. ? input sda serial data: the sda pin is an open-drain bidirectional input/output pin used to serially transfer data to and from the device. the sda pin must be pulled-high using an external pull-up resistor and may be wire-anded with any number of other open-drain or open-collector pins from other devices on the same bus. ? input/output alert alert: the alert pin is an open-drain output pin used to indicate when the temperature goes beyond the user-programmed temperature limits. the alert pin can be operated in one of two different modes (interrupt or comparator mode) as defined by the cmp/int bit in the configuration register. the alert pin defaults to an active-low output upon device power-up or reset but can be reconfigured as an active-high output by setting the pol bit in the configuration register. this pin can be wire-anded together with alert pins from other devices on the same bus. when wire-anding pins together, the alert pin should be configured as an active-low output so that when a single alert pin on the common alert bus goes active, the entire common alert bus will go low and the host controller will be properly notified since other alert pins that may be in the inactive-high state will not mask the true alert signal. in an smbus environment, the smbus host can respond by sending an smbus ara (alert response address) command to determine which device on the smbus generated the alert signal. the alert pin must be pulled-high using an external pull-up resistor even when it is not used. care must also be taken to prevent this pin from being shorted directly to ground without a resistor at any time whether during testing or normal operation. ? output a 2-0 address inputs: the a 2-0 pins are used to select the device address and correspond to the three least-significant bits (lsbs) of the i 2 c/smbus 7-bit slave address. these pins can be directly connected in any combination to v cc or gnd, and by utilizing the a 2-0 pins, up to eight devices may be addressed on a single bus. the a 2-0 pins are internally pulled to gnd and may be left floating; however, it is highly recommended that the a 2-0 pins always be directly connected to v cc or gnd to ensure a known address state. ? input v cc device power supply: the v cc pin is used to supply the source voltage to the device. operations at invalid v cc voltages may produce spurious results and should not be attempted. ? power gnd ground: the ground reference for the power supply. gnd should be connected to the system ground. ? power
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 6 figure 1. pin configurations 3. block diagram figure 3-1. block diagram 8-soic (top view) 8-msop (top view) 8-udfn (top view) sda scl a lert gnd v cc a 0 a 1 a 2 sda scl alert gnd sda scl alert gnd v cc a 0 a 1 a 2 v cc a 0 a 1 a 2 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 1 2 3 4 8 7 6 5 scl sda a 2-0 a lert 3 digital comparator a/d converter temperature sensor temperature register t low limit register t high limit register configuration register pointer register i 2 c/smbus interface control and logic nonvolatile configuration register nonvolatile t high limit register nonvolatile t low limit register
7 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 4. device communication the AT30TS750A operates as a slave device and utilizes a simple 2-wire i 2 c and smbus compatible digital serial interface to communicate with a host controller, commonly referred to as the bus master. the master initiates and controls all read and write operations to the slave devices on the serial bus, and both the master and the slave devices can transmit and receive data on the bus. the serial interface is comprised of just two signal lines: serial clock (scl) and serial data (sda). the scl pin is used to receive the clock signal from the master, while the bidirectional sda pin is used to receive command and data information from the master as well as to send data back to the master. data is always latched into the AT30TS750A on the rising edge of scl and always output from the device on the falling edge of scl. both the scl and sda pin incorporate integrated spike suppression filters and schmitt triggers to minimize the effects of input spikes and bus noise. all command and data information is transferred with the most-significant bit (msb) first. during bus communication, one data bit is transmitted every clock cycle, and after eight bits (one byte) of data has been transferred, the receiving device must respond with either an acknowledge (ack) or a no-acknowledge (nack) response bit during a ninth clock cycle (ack/nack clock cycle) generated by the master; therefore, nine clock cycles are required for every one byte of data transferred. there are no unused clock cycles during any read or write operation, so there must not be any interruptions or breaks in the data stream during each data byte transfer and ack or nack clock cycle. during data transfers, data on the sda pin must only change while scl is low, and the data must remain stable while scl is high. if data on the sda pin changes while scl is high, then either a start or a stop condition will occur. start and stop conditions are used to initiate and end all serial bus communication between the master and the slave devices. the number of data bytes transferred between a start and a stop condition is not limited and is determined by the master. in order for the serial bus to be idle, both the scl and sda pins must be in the logic-high state at the same time. 4.1 start condition a start condition occurs when there is a high-to-low transition on the sda pin while the scl pin is stable in the logic-high state. the master uses a start condition to initiate any data transfer sequence, and the start condition must precede any command. the AT30TS750A will continuously monitor the sda and scl pins for a start condition, and the device will not respond unless one is given. 4.2 stop condition a stop condition occurs when there is a low-to-high transition on the sda pin while the scl pin is stable in the logic-high state. the master uses the stop condition to end a data transfer sequence to the AT30TS750A which will subsequently return to the idle state. the master can also utilize a repeated start condition instead of a stop condition to end the current data transfer if the master will perform another operation. 4.3 acknowledge (ack) after every byte of data received, the AT30TS750A must acknowledge to the master that it has successfully received the data byte by responding with an ack. this is accomplished by the master first releasing the sda line and providing the ack/nack clock cycle (a ninth clock cycle for every byte). during the ack/nack clock cycle, the AT30TS750A must output a logic 0 (ack) for the entire clock cycle such that the sda line must be stable in the logic-low state during the entire high period of the clock cycle.
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 8 4.4 no-acknowledge (nack) when the AT30TS750A is transmitting data to the master, the master can indicate that it is done receiving data and wants to end the operation by sending a nack response to the AT30TS750A instead of an ack response. this is accomplished by the master outputting a logic 1 during the ack/nack clock cycle, at which point the AT30TS750A will release the sda line so that the master can then generate a stop condition. in addition, the AT30TS750A can use a nack to respond to the master instead of an ack for certain invalid operation cases such as an attempt to write to a read-only register (e.g. an attempt to write to the temperature register). figure 4-1. start, stop, and ack scl sda start condition data change allowed data change allowed data change allowed data change allowed ack stop condition data must be stable data must be stable data must be stable 1 28 9
9 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 5. device operation commands used to configure and control the operation of the AT30TS750A are sent to the device from the master via the serial interface. likewise, the master can read the temperature data from the AT30TS750A via the serial interface; however, since multiple slave devices can reside on the serial bus, each slave device must have its own unique 7-bit address so that the master can access each device independently. for the AT30TS750A, the first four msbs of its 7-bit address are the device type identifier and are fixed at 1001. the remaining three lsbs correspond to the states of the hard-wired a 2-0 address pins. example: if the a 2-0 pins are connected to gnd, then the 7-bit device address would be 1001000. in order for the master to select and access the AT30TS750A, the master must first initiate a start condition. following the start condition, the master must output the device address byte. the device address byte consists of the 7-bit device address plus a read/write (r/ w) control bit, which indicates whether the master will be performing a read or a write to the AT30TS750A. if the r/ w control bit is a logic 1, then the master will be reading data from the AT30TS750A. alternatively, if the r/ w control bit is a logic 0, then the master will be writing data to the AT30TS750A. table 5-1. AT30TS750A address byte if the 7-bit address sent by the master matches that of the AT30TS750A, then the device will respond with an ack after it has received the full address byte. if there is an address mismatch, then the AT30TS750A will respond with a nack and return to the idle state. 5.1 temperature measurements the AT30TS750A utilizes a band-gap type temperature sensor with an internal sigma-delta analog-to-digital converter (adc) to measure and convert the temperature reading into a digital value with a selectable resolution as high as 0.0625 ? c. the measured temperature is calibrated in degrees celsius; therefore, a lookup table or conversion routine is necessary for applications that wish to deal in degrees fahrenheit. the result of the digitized temperature measurements are stored in the internal temperature register of the AT30TS750A, which is readable at any time through the device's serial interface. when in the normal operating mode, the device performs continuous temperature measurements and updates the contents of the temperature register (see section 6.2, ?temperature register? on page 16 ) after each analog-to-digital conversion. the resolution of the temperature measurement data can be configured to 9, 10, 11, or 12 bits which corresponds to temperature increments of 0.5 ? c, 0.25 ? c, 0.125 ? c, and 0.0625 ? c, respectively. selecting the temperature resolution is done by setting the r1 and r0 bits in the configuration register (see section 6.3, ?configuration register? on page 18 ). the adc conversion time does increase with each bit of higher resolution, so careful consideration should be given to the resolution versus conversion time relationship. the resolution after device power-up or reset will revert to what was previously selected using the nvr1 and nvr0 bits of the nonvolatile configuration register bits prior to when the device was powered-down or reset. with 12 bits of resolution, the AT30TS750A can theoretically measure a temperature range of 255 ? c (-128 ? c to +127 ? c); however, the device is only designed to measure temperatures over a range of -55 ? c to +125 ? c. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 device type identifier device address read/write 1 0 0 1 a2 a1 a0 r/ w
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 10 5.2 temperature alarm after the measured temperature value has been stored into the temperature register, the data will be compared with both the high and low temperature limits defined by the values stored in the t high limit register and t low limit register. if the comparison results in a valid fault condition (see section 5.2.1, ?fault tolerance limits? on page 10 ), then the device will activate the alert output pin. the polarity and function of the alert pin can be configured by using specific bits in the configuration register. the polarity of the alert pin is controlled by the pol bit in the configuration register while the function of the alert pin changes based on the alarm thermostat mode, which can be configured to either comparator mode (see section 5.2.2, ?comparator mode? on page 11 ) or interrupt mode (see section 5.2.3, ?interrupt mode? on page 12 ) by using the cmp/int bit in the configuration register. after the device powers up or resets, the nvpol and nvcmp/int bits of the nonvolatile configuration register are automatically copied into the pol and cmp/int bits of the configuration register; therefore, the alert pin polarity and function will revert back to the settings defined by the nvpol and nvcmp/int bits prior to when the device was powered-down or reset. the value of the high temperature limit stored in the t high limit register must be greater than the value of the low temperature limit stored in the t low limit register in order for the alert function to work properly; otherwise, the alert pin will output erroneous results and will falsely signal temperature alarms. 5.2.1 fault tolerance limits a temperature fault occurs if the measured temperature meets or exceeds either the high temperature limit set by the t high limit register or the low temperature limit set by the t low limit register. to prevent false alarms due to environmental or temperature noise, the device incorporates a fault tolerance queue that requires consecutive temperature faults to occur before resulting in a valid fault condition. the fault tolerance queue value is controlled by the ft1 and ft0 bits in the configuration register and can be set to a single fault count of one or a count of two, four, or six consecutive faults. an internal counter that automatically increments after a temperature fault is used to determine if the fault tolerance queue setting has been met. after incrementing the fault counter, the device will compare the count to the fault tolerance queue setting to see if a valid fault condition should be triggered. once a valid fault condition occurs, the device will activate the alert output pin. if the most recent measured temperature does not meet or exceed the high or low temperature limit, then the internal fault counter will be reset back to zero. figure 5-1 shows a sample temperature profile and how each temperature fault would impact the internal fault counter. figure 5-1. fault count example after the device powers up or resets, the nvft1 and nvft0 bits of the nonvolatile configuration register are automatically copied into the ft1 and ft0 bits of the configuration register; therefore, the fault tolerance queue setting will revert back to the settings defined by the nvft1and nvft0 bits prior to when the device was powered down or reset. temperature measurements/conversions t high limit temperature t low limit
11 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 5.2.2 comparator mode when the device operates in the comparator mode, then the alert pin goes active if the measured temperature meets or exceeds the high temperature limit set by the t high limit register and a valid fault condition exists (the consecutive number of temperature faults has been reached). the alert pin will return to the inactive state after the measured temperature drops below the t low limit register value the appropriate number of times to create a subsequent valid fault condition. the alert pin only changes state based on the high and low temperature limits and fault conditions; reading from or writing to any register or putting the device into shutdown mode will not affect the state of the alert pin. the high temperature limit set by the t high limit register must be greater than the low temperature limit set by the t low limit register in order for the alert pin to activate correctly. if switching from interrupt mode to comparator mode while the alert pin is already active, then the alert pin will remain active until the measured temperature is below the t low limit register value the appropriate number of times to create a valid fault condition. the alert pin will return to the inactive state if the device receives the general call reset command. when reset, the contents of the nonvolatile configuration register will be copied into the configuration register; therefore, the device may or may not return to the comparator mode depending on the setting of the nvcmp/int bit in the nonvolatile configuration register. figure 5-2 illustrates both the active high and active low alert pin response for a sample temperature profile with the device configured for the comparator mode and a fault tolerance queue setting of two. figure 5-2. comparator mode (fault tolerance queue = 2) temperature measurements/conversions t high limit temperature t low limit alert (active high, pol = 1) alert (active low, pol = 0)
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 12 5.2.3 interrupt mode similar to the comparator mode, when the device operates in the interrupt mode, the alert pin will go active if the measured temperature meets or exceeds the high temperature limit set by the t high limit register and a valid fault condition exists (the consecutive number of temperature faults has been reached). unlike the comparator mode, however, the alert pin will remain active until one of three normal operation events takes place: any one of the device's registers is read, the device responds to an smbus alert response address (ara), or the device is put into shutdown mode. once the alert pin returns to the inactive state, it will not go active again until the measured temperature drops below the low temperature limit set by the t low limit register for the appropriate number of consecutive faults. again, the alert pin will remain active until one of the device's registers is read, the device responds to an smbus ara, or the device is placed into the shutdown mode. after the alert pin becomes inactive again, the cycle will repeat itself with the alert pin going active after the measured temperature meets or exceeds the t high limit register value for the proper number of consecutive faults. this process is cyclical between t high and t low temperature alarms (e.g. t high event, alert clear, t low event, alert clear, t high event, alert clear, t low event, etc.). in order for the alert pin to normally become active for the first time in the interrupt mode, the first event must be a t high temperature alarm event; therefore, even if the measured temperature initially starts off between the t high and t low limits and then drops below the t low temperature limit and has met valid fault conditions, the alert pin will still not go active. the high temperature limit set by the t high limit register must be greater than the low temperature limit set by the t low limit register in order for the alert pin to activate correctly. if switching from comparator mode to interrupt mode while the alert pin is already active, then the alert pin will remain active until it is cleared by one of the events already detailed: any one of the device's registers is read, the device responds to an smbus alert response address (ara), or the device is put into shutdown mode. the alert pin will also return to the inactive state if the device receives the general call reset command. when reset, the contents of the nonvolatile configuration register will be copied into the configuration register; therefore, the device may or may not return to the interrupt mode depending on the setting of the nvcmp/int bit in the nonvolatile configuration register. figures 5-3 and figure 5-4 show both the active high and active low alert pin response for a sample temperature profile with the device configured for the interrupt mode and a fault tolerance queue setting of two. figure 5-4 illustrates how the alert pin output would look if there was a longer delay between the alert trigger and the reading of a register. figure 5-3. interrupt mode (fault tolerance queue = 2) temperature measurements/conversions t high limit temperature t low limit alert (active high, pol = 1) alert (active low, pol = 0) read register read register read register
13 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 figure 5-4. interrupt mode (fault tolerance queue = 2) delay before reading register 5.3 shutdown mode to reduce current consumption and save power, the device features a shutdown mode that disables all internal device circuitry except for the serial interface and por circuits. while in the shutdown mode, the internal temperature sensor is not active, so no temperature measurements will be made. entering and exiting the shutdown mode is controlled by the sd bit in the configuration register. entering the shutdown mode can affect the alert pin depending on the alarm thermostat mode. if the device is configured to operate in the interrupt mode, then the alert pin will go inactive when the device enters the shutdown mode; however, the alert pin will not change states if the device is operating in the comparator mode. the fault count information will not change when the device enters or exits the shutdown mode; therefore, the number of previous temperature faults recorded by the internal fault counter will be retained unless the device is power-cycled or reset. when exiting the shutdown mode, the alert pin will go active if operating in interrupt mode, a valid fault condition exists, and the t high and t low event cycles are maintained (i.e. t high event before entering shutdown mode followed by a t low event when exiting shutdown mode). the device can be powered-down while in the shutdown mode so that it will remain in the shutdown mode after the subsequent power-up operation. this is accomplished by setting the nvsd bit in the nonvolatile configuration register to the logic 1 state prior to power-down. upon power-up or reset, the device will first copy the contents of the nonvolatile data registers into the volatile data registers, after which the device will perform a single temperature measurement and store the result in the temperature register. after this process is complete, the device will re-enter the shutdown mode. 5.3.1 one-shot mode the AT30TS750A features a one-shot temperature mode that allows the device to perform a single temperature measurement while in the shutdown mode. by keeping the device in the shutdown mode and utilizing the one-shot mode, the AT30TS750A can remain in a lower power state and only go active to take temperature measurements on an as-needed basis. the internal fault counter will be updated when taking a temperature measurement using the one-shot mode; therefore, a valid fault condition can be generated by the one-shot temperature measurements. if operating in comparator mode, then the fault condition will cause the alert pin to go either active or inactive depending on if the fault condition is a result of a t high or t low event. if operating in interrupt mode, the fault condition will cause the alert pin to pulse active for a short duration of time to indicate a t high or t low event has occurred. the alert pin will then return to the inactive state. the one-shot mode is controlled using the os bit in the configuration register (see section 6.3.1, ?os bit? on page 19 ). temperature measurements/conversions t high limit temperature t low limit alert (active high, pol = 1) alert (active low, pol = 0) read register read register
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 14 6. registers the AT30TS750A contains eight registers (a pointer register and seven data registers) that are used to control the operational mode and performance of the temperature sensor, store the user-defined high and low temperature limits, and store the digitized temperature measurements. all accesses to the device are performed using these eight registers. in order to read from and write to one of the device's seven data registers, the user must first select a desired data register by utilizing the pointer register. the device incorporates both volatile and nonvolatile versions of the configuration register, the t low limit register, and the t high limit register. upon device power-up or reset, the AT30TS750A will copy the contents of the nonvolatile data registers into the volatile data registers. both the volatile and nonvolatile data registers can be modified separately provided that the registers are not locked or locked down; however, all temperature sensor related operations, such as responses to high and low temperature conditions, are based on the settings stored in the volatile versions of the registers only. therefore, if the nonvolatile data registers are updated with new values, then the contents of the nonvolatile data registers should be copied to the volatile data registers (see section 9.1, ?copy nonvolatile registers to volatile registers? on page 32 ) table 6-1. registers the configuration register, despite being 16-bits wide, is compatible to industry standard lm75-type temperature sensors that use an 8-bit wide register in that only the first 8-bits of the configuration register need to be written to or read from. 6.1 pointer register the 8-bit write-only pointer register is used to address and select which one of the device's seven data registers (temperature register, configuration register, t low limit register, t high limit register, nonvolatile configuration register, nonvolatile t low limit register, or nonvolatile t high limit register) will be read from or written to. for read operations from the AT30TS750A, once the pointer register is set to point to a particular data register, it remains pointed to that same data register until the pointer register value is changed. example: if the user sets the pointer register to point to the temperature register, then all subsequent reads from the device will output data from the temperature register until the pointer register value is changed. register address read/write size power-on default factory default pointer register n/a w 8-bit 00h n/a temperature register 00h r 16-bit 0000h n/a configuration register 01h r/w 16-bit copy of nonvolatile configuration register n/a t low limit register 02h r/w 16-bit copy of nonvolatile t low limit register n/a t high limit register 03h r/w 16-bit copy of nonvolatile t high limit register n/a nonvolatile configuration register 11h r/w 16-bit last programmed state 0000h nonvolatile t low limit register 12h r/w 16-bit last programmed state 4b00h (75 ? c) nonvolatile t high limit register 13h r/w 16-bit last programmed state 5000h (80 ? c)
15 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 for write operations to the AT30TS750A, the pointer register value must be refreshed each time a write to the device is to be performed, even if the same data register is going to be written to a second time in a row. example: if the pointer register is set to point to the configuration register, once the subsequent write operation to the configuration register has completed, the user cannot write again into the configuration register without first setting the pointer register value again. as long as a write operation is to be performed, the device will assume that the pointer register value is the first data byte received after the address byte. since only seven data registers are available for access, only the five lsbs (p4-p0) of the pointer register are used; the remaining three bits (p7-p5) of the pointer register should always be set to zero to allow for future migration paths to other temperature sensor devices that have more than seven data registers. in addition, the device incorporates additional commands that are decoded in lieu of the pointer register byte; therefore, if bits p7-p5 are not set as zero when setting the value of the pointer register byte, the device may interpret the data as one of the additional commands. table 6-2 shows the bit assignments of the pointer register and the associated pointer addresses of the data registers available. attempts to write any values other than those listed in table 6-2 into the pointer register will be ignored by the device, and the contents of the pointer register will not be changed. the device will respond back to the master with a nack to indicate that the device received an invalid pointer register byte. table 6-2. pointer register and address assignments to set the value of the pointer register, the master must first initiate a start condition followed by the AT30TS750A device address byte (1001aaa0 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the AT30TS750A has received the proper address byte, the device will send an ack to the master. the master must then send the appropriate data byte to the AT30TS750A to set the value of the pointer register. after device power-up or reset, the pointer register defaults to 00h which is the temperature register location; therefore, the temperature register can be read from immediately after device power-up or reset without having to set the pointer register. if the device is configured to power-up in the shutdown mode, then the device will make a single temperature measurement immediately after power-up so that valid temperature data can be output from the temperature register. figure 6-1. write pointer register pointer register value associated address register selected p7 p6 p5 p4 p3 p2 p1 p0 0 0 0 0 0 0 0 0 00h temperature register 0 0 0 0 0 0 0 1 01h configuration register 0 0 0 0 0 0 1 0 02h t low limit register 0 0 0 0 0 0 1 1 03h t high limit register 0 0 0 1 0 0 0 1 11h nonvolatile configuration register 0 0 0 1 0 0 1 0 12h nonvolatile t low limit register 0 0 0 1 0 0 1 1 13h nonvolatile t high limit register sck sda address byte pointer register byte start by master ack from slave msb msb ack from slave stop by master 1 0 0 1 a a a 0 0 p7 p6 p5 p4 p3 p2 p1 p0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 16 6.2 temperature register the temperature register is a 16-bit read-only register that stores the digitized value of the most recent temperature measurement. the temperature data value is represented in the twos complement format, and, depending on the resolution selected, up to 12 bits of data will be available for output with the remaining lsbs being fixed in the logic 0 state. the temperature register can be read at any time, and since temperature measurements are performed in the background, reading the temperature register does not affect any other operation that may be in progress. the msb (bit 15) of the temperature register contains the sign bit of the measured temperature value with a zero indicating a positive number and a one indicating a negative number. the remaining msbs of the temperature register contain the temperature value in the twos complement format. table 6-3 details the temperature register format for the different selectable resolutions, and table 6-4 shows some examples for 12-bit resolution temperature register data values and the associated temperature readings. table 6-3. temperature register format note: td = temperature data table 6-4. 12-bit resolution temperature data/values examples resolution upper byte lower byte bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12 bits sign td td td td td td td td td td td 0 0 0 0 11 bits sign td td td td td td td td td td 0 0 0 0 0 10 bits sign td td td td td td td td td 0 0 0 0 0 0 9 bits sign td td td td td td td td 0 0 0 0 0 0 0 temperature temperature register data binary value hex value +125c 0111 1101 0000 0000 7d00h +100c 0110 0100 0000 0000 6400h +75c 0100 1011 0000 0000 4b00h +50.5c 0011 0010 1000 0000 3280h +25.25c 0001 1001 0100 0000 1940h +10.125c 0000 1010 0010 0000 0a20h +0.0625c 0000 0000 0001 0000 0010h 0c 0000 0000 0000 0000 0000h -0.0625c 1111 1111 1111 0000 fff0h -10.125c 1111 0101 1110 0000 f5e0h -25.25c 1110 0110 1100 0000 e6c0h -50.5c 1100 1101 1000 0000 cd80h -55c 1100 1001 0000 0000 c900h
17 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 after each temperature measurement and digital conversion is complete, the new temperature data is loaded into the temperature register if the register is not currently being read. if a read is in progress, then the previous temperature data will be output. in order to read the most recent temperature measurement data, the pointer register must be set or have been previously set to 00h. if the pointer register has already been set to 00h, the temperature register can be read by having the master first initiate a start condition followed by the AT30TS750A device address byte (1001aaa1 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the AT30TS750A has received the proper address byte, the device will send an ack to the master. the master can then read the upper byte of the temperature register. after the upper byte of the temperature register has been clocked out of the AT30TS750A, the master must send an ack to indicate that it is ready for the lower byte of the temperature data. the AT30TS750A will then clock out the lower byte of the temperature register, after which the master must send a nack to end the operation. when the AT30TS750A receives the nack, it will release the sda line so that the master can send a stop or repeated start condition. if the master does not send a nack but instead sends an ack after the lower byte of the temperature register has been clocked out, then the device will repeat the sequence by outputting new temperature data starting with the upper byte of the temperature register. if 8-bit temperature resolution is satisfactory, then the lower byte of the temperature register does not need to be read. in this case, the master would send a nack instead of an ack after the upper byte of the temperature register has been clocked out of the AT30TS750A. when the AT30TS750A receives the nack, the device will know that it should not send out the lower byte of the temperature register and will instead release the sda line so the master can send a stop or repeated start condition. the temperature register defaults to 0000h after device power-up or reset; therefore, the system should wait the maximum conversion time (t conv ) for the selected resolution before attempting to read valid temperature data. if the device is configured to power-up in the shutdown mode, then the device will make a single temperature measurement immediately after power-up so that valid temperature data can be output from the temperature register after the maximum t conv time. since the temperature register is a read-only register, any attempts to write to the register will be ignored, and the device will subsequently respond by sending a nack back to the master for any data bytes that are sent. figure 6-2. read temperature register ? 16 bits note: assumes the pointer register was previously set to point to the temperature register. figure 6-3. read temperature register ? 8 bits note: assumes the pointer register was previously set to point to the temperature register. sck sda address byte temperature register upper byte temperature register lower byte start by master ack from slave ack from master msb msb nack from master stop by master msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 1 0 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 1 sck sda address byte temperature register upper byte start by master ack from slave msb msb nack from master stop by master 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 1 0 d15 d14 d13 d12 d11 d10 d9 d8 1
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 18 6.3 configuration register the configuration register is used to control key operational modes and settings of the device such as the one-shot mode, the temperature conversion resolution, the fault tolerance queue, the alert pin polarity, the alarm thermostat mode, and the shutdown mode. the configuration register is a 16-bit wide read/write register; however, only the first 8-bits of the register are actually used while the least-significant 8-bits are reserved for future use to provide an upward migration path to other temperature sensor devices that have enhanced features. since only the most-significant 8-bits of the configuration register are used, the device is backwards compatible to industry standard lm75-type temperature sensors that use 8-bit wide registers. after device power-up or reset, the contents of the most-significant byte (bits 15 through 8) of the nonvolatile configuration register will always be automatically copied into the configuration register; therefore, the configuration register settings will match the settings of the nonvolatile configuration register prior to when the device was powered- down or reset. since the configuration register value will always be copied from the nonvolatile configuration register, the configuration register can be temporarily changed without affecting subsequent power-up/reset settings. if it is desired for the new configuration register settings to become the new power-up/reset settings, then the contents of the configuration register can be copied into the most-significant byte of the nonvolatile configuration register by using the copy volatile registers to nonvolatile registers command (see section 9.2, ?copy volatile registers to nonvolatile registers? on page 33 ). note: when using the copy volatile registers to nonvolatile registers command, the contents of the t high and t low limit registers will also be copied into the nonvolatile t high and t low limit registers. table 6-5. configuration register bit name type description 15 os one-shot mode r/w 0 normal operation (default) 1 perform one-shot measurement (valid in shutdown mode only) 14:13 r1:r0 conversion resolution r/w 00 9-bits (default) 01 10-bits 10 11-bits 11 12-bits 12:11 ft1:ft0 fault tolerance queue r/w 00 alarm after 1 fault (default) 01 alarm after 2 consecutive faults 10 alarm after 4 consecutive faults 11 alarm after 6 consecutive faults 10 pol alert pin polarity r/w 0 alert pin is active low (default) 1 alert pin is active high 9 cmp/int alarm thermostat mode r/w 0 comparator mode (default) 1 interrupt mode 8 sd shutdown mode r/w 0 temperature sensor performing active measurements (default) 1 temperature sensor disabled and device in shutdown mode 7:1 rfu reserved for future use r 0 reserved for future use 0 nvrbsy nonvolatile registers busy r 0 nonvolatile registers are ready for access. 1 nonvolatile registers are busy and cannot be read from or written to.
19 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 to set the value of the configuration register, the master must first initiate a start condition followed by the AT30TS750A's device address byte (1001aaa0 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the AT30TS750A has received the proper address byte, the device will send an ack to the master. the master must then send the appropriate pointer register byte of 01h to select the configuration register. after the pointer register byte of 01h has been sent, the AT30TS750A will send another ack to the master. after receiving the ack from the AT30TS750A, the master must then send the appropriate data byte to the AT30TS750A to set the value of the configuration register. only the first data byte sent to the AT30TS750A will be recognized as valid data; any subsequent bytes received by the device will simply be ignored. if the master does not send a complete byte of configuration register data prior to issuing a stop or repeated start condition, then the AT30TS750A will ignore the data and the contents of the configuration register will be unchanged. in addition to the master not sending a complete byte of configuration register data, writing to the configuration register will be ignored and no operation will be performed if the volatile and nonvolatile registers are currently locked (the rlck bit of the nonvolatile configuration register is in the logic 1 state) or the volatile and nonvolatile registers are permanently locked down (the rlckdwn bit of the nonvolatile configuration register is in the logic 1 state). however, the device will still respond with an ack to indicate that it received the proper data byte even though the contents of the configuration register will not be changed. 6.3.1 os bit the os bit is used to enable the one-shot temperature measurement mode. when a logic 1 is written to the os bit while the AT30TS750A is in the shutdown mode, the device will become active and perform a single temperature measurement and conversion. after the temperature register has been updated with the measured temperature data, the device will return to the low-power shutdown mode and clear the os bit. writing a one to the os bit when the device is not in the shutdown mode will have no affect. when reading the configuration register, the os bit will always be read as a logic 0. 6.3.2 r1:r0 bits the r1 and r0 bits are used to select the conversion resolution of the internal sigma-delta adc. four possible resolutions can be set to maximize for either higher resolution or faster conversion times. the r1 and r0 bits will be copied from the nvr1 and nvr0 in the nonvolatile configuration register after device power-up or reset, allowing the device to retain the conversion resolution that was previously set by the nonvolatile configuration register prior to power-down or reset. table 6-6. conversion resolution r1 r0 conversion resolution conversion time 0 0 9 bits 0.5c 25ms 0 1 10 bits 0.25c 50ms 1 0 11 bits 0.125c 100ms 1 1 12 bits 0.0625c 200ms
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 20 6.3.3 ft1:ft0 bits the ft1 and ft0 bits are used to set the fault tolerance queue value which defines how many consecutive faults must occur before the alert pin will be activated (see section 5.2.1, ?fault tolerance limits? on page 10 ). the ft1 and ft0 bit settings provide four different fault values as detailed in table 6-7 . after the device powers up or resets, the ft1 and ft0 bits will be copied from the nvft1 and nvft0 in the nonvolatile configuration register; therefore, the fault tolerance queue value will default to whatever value was previously stored in the nonvolatile configuration register prior to configuration register power-down or reset. table 6-7. fault tolerance queue 6.3.4 pol bit the alert pin polarity is controlled by the pol bit. when the pol bit is in the logic 0 state, the alert pin will be an active low output. to configure the alert pin as an active high output, the pol bit must be set to the logic 1 state. after the device powers up or resets, the pol bit will be copied from the nvpol bit in the nonvolatile configuration register; therefore, the polarity of the alert pin will default to the state defined by the nonvolatile configuration register prior to power-down or reset. 6.3.5 cmp/int bit the cmp/int bit controls whether the device will operate in the comparator mode or the interrupt mode. setting the cmp/int bit to the logic 0 state will put the device into the comparator mode. alternatively, when the cmp/int bit is set to the logic 1 state, then the device will operate in the interrupt mode. the function of the alert pin changes based on the cmp/int bit setting. the cmp/int bit will be copied from the nvcmp/int bit in the nonvolatile configuration register after the device powers up or resets. since the cmp/int bit is copied from the nvcmp/int bit, the device will default to whatever mode was selected by the nonvolatile configuration register prior to power-down or reset. 6.3.6 sd bit the sd bit is used to enable or disable the device's shutdown mode. when the sd bit is in the logic 0 state, the device will be in the normal operational mode and perform continuous temperature measurements and conversions. when the sd bit is set to the logic 1 state, the device will finish the current temperature measurement and conversion and will store the result in the temperature register, after which the device will then enter the shutdown mode. resetting the sd bit back to a logic 0 will return the device to the normal operating mode. after the device powers up or resets, the sd bit will be copied from the nvsd bit in the nonvolatile configuration register; therefore, it is possible for the device to automatically enter the shutdown mode after power-up or reset by setting the nvsd bit to the logic 1 state prior to power-down or reset. see section 5.3, ?shutdown mode? on page 13 for more details. ft1 ft0 consecutive faults required 0 0 1 0 1 2 1 0 4 1 1 6
21 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 6.3.7 nvrbsy the ready/busy status of the nonvolatile configuration register, nonvolatile t low limit register, and nonvolatile t high limit register can be determined by reading the nvrbsy bit. when the nvrbsy bit is in the logic 0 state, then the nonvolatile configuration and limit registers are available to be read from or written to. when the nvrbsy bit is in the logic 1 state, the nonvolatile registers are busy and cannot be accessed for reading, writing, or copying. attempting to read the nonvolatile registers while the registers are busy will result in erroneous data being output. similarly, any attempts to write to one of the nonvolatile registers while the nvrbsy bit is in the logic 1 state will result in the data being ignored. both the copy nonvolatile registers to volatile registers and the copy volatile registers to nonvolatile registers commands will also be ignored when the nvrbsy bit is in the logic 1 state. for more details and a complete list of commands that are and are not allowed while nvrbsy is in the logic 1 state, see section 8., ?operations allowed during nonvolatile busy status? on page 31 . figure 6-4. write to configuration register figure 6-5. read from configuration register note: assumes the pointer register was previously set to point to the configuration register. sck sda address byte pointer register byte configuration register upper byte start by master ack from slave ack from slave msb msb ack from slave stop by master msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 0 0 0 0 0 0 0 0 0 1 0 d15 d14 d13 d12 d11 d10 d9 d8 0 sck sda start by master ack from slave nack from master address byte configuration register upper byte stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 1 0 d15 d14 d13 d12 d11 d10 d9 d8 1
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 22 6.4 nonvolatile configuration register the nonvolatile configuration register is a 16-bit wide read/write register used to manage key power-up/reset device settings and operational modes including the locking of the AT30TS750A's various registers. the nonvolatile configuration register is used in conjunction with the configuration register to control how the device operates. all bits in the nonvolatile configuration register will retain their state even after the device has been powered down or reset. on every power-up or reset sequence, the contents of the most-significant byte (bits 15 through 8) of the nonvolatile configuration register will be copied into the configuration register, after which all device operations and settings will then be controlled by the configuration register. by utilizing the nonvolatile configuration register, the device can power-up or reset in a pre-defined, user-selected operating mode (e.g. comparator mode, shutdown mode, etc.) with pre-defined settings (e.g. 12-bit resolution, alert pin active high, etc.); therefore, unlike standard lm75-type temperature sensors, there is no need to update the configuration register settings after every power-up or reset. since the nonvolatile configuration register utilizes nonvolatile storage cells, care must be taken when updating the register to accommodate the aspects of an associated program time and finite program endurance limit. power must not be removed from the device during the internally self-timed programming cycle of the register. if power is removed prior to the completion of the programming cycle, then the contents of the register cannot be guaranteed. in addition, the contents of the register may become corrupt if it is programmed more than the maximum allowed number of writes. table 6-8. nonvolatile configuration register bit name type description 15 nu not used r 0 not used. 14:13 nvr1:nvr0 conversion resolution r/w 00 9-bits (factory default) 01 10-bits 10 11-bits 11 12-bits 12:11 nvft1:nvft0 fault tolerance queue r/w 00 alarm after 1 fault (factory default). 01 alarm after 2 consecutive faults. 10 alarm after 4 consecutive faults. 11 alarm after 6 consecutive faults. 10 nvpol alert pin polarity r/w 0 alert pin is active low (factory default). 1 alert pin is active high. 9 nvcmp/int alarm thermostat mode r/w 0 comparator mode (factory default). 1 interrupt mode. 8 nvsd shutdown mode r/w 0 temperature sensor performing active measurements (factory default). 1 temperature sensor disabled and device in shutdown mode. 7:3 rfu reserved for future use 0 reserved for future use. 2 rlckdwn register lockdown r/w 0 all configuration and limit registers are not locked down (factory default). 1 all configuration and limit registers are permanently locked down (rom) and can never be modified again. 1 rlck register lock r/w 0 all configuration and limit registers are unlocked and can be modified (factory default). 1 all configuration and limit registers are locked and cannot be modified. 0 rfu reserved for future use r 0 reserved for future use.
23 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 to set the value of the nonvolatile configuration register, the master must first initiate a start condition followed by the AT30TS750A device address byte (1001aaa0 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the AT30TS750A has received the proper address byte, the device will send an ack to the master. the master must then send the appropriate pointer register byte of 11h to select the nonvolatile configuration register. after the pointer register byte of 11h has been sent, the AT30TS750A will send another ack to the master. after receiving the ack from the AT30TS750A, the master must then send two data bytes to the AT30TS750A to set the value of the nonvolatile configuration register. any subsequent bytes sent to the AT30TS750A will simply be ignored by the device. if the master does not send two complete bytes of nonvolatile configuration register data prior to issuing a stop or repeated start condition, then the AT30TS750A will ignore the data and the contents of the nonvolatile configuration register will not be changed. after the master has issued a stop or repeated start condition, the AT30TS750A will begin the internally self-timed program operation, and the contents of the nonvolatile configuration register will be updated within a time of t prog . during this time, the nvrbsy bit in the configuration register will indicate that the device is busy. if the master issues a repeated start condition instead of a stop condition, the AT30TS750A will abort the operation and the contents of the nonvolatile configuration register will not be changed. in addition to the master not sending two complete bytes of data, writing to the nonvolatile configuration register will be ignored and no operation will be performed under the following conditions: the nonvolatile registers are already busy (the nvrbsy bit of the configuration register is in the logic 1 state), the volatile and nonvolatile registers are currently locked (the rlck bit of the nonvolatile configuration register is in the logic 1 state), or the volatile and nonvolatile registers are permanently locked down (the rlckdwn bit of the nonvolatile configuration register is in the logic 1 state). however, the device will still respond with an ack, except in the case of the nonvolatile registers being busy, to indicate that it received the proper data bytes even though the program operation will not be performed. in the case of the nonvolatile registers being busy, the device will respond with an ack to the address and pointer bytes but will then nack when the data bytes are sent from the master. 6.4.1 nvr1: nvr0 bits the nonvolatile nvr1 and nvr0 bits are used to select the power-up/reset default conversion resolution of the internal sigma-delta adc. four possible resolutions can be set to maximize for either higher resolution or faster conversion times. the nvr1 and nvr0 bits are set from the factory to default to the logic 0 state to retain backwards compatibility to industry-standard lm75-type devices. table 6-9. conversion resolution nvr1 nvr0 conversion resolution conversion time 0 0 9 bits 0.5c 25ms 0 1 10 bits 0.25c 50ms 1 0 11 bits 0.125c 100ms 1 1 12 bits 0.0625c 200ms
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 24 6.4.2 nvft1:nvft0 bits the nonvolatile nvft1 and nvft0 bits are used to set the power-up/reset default fault tolerance queue value which defines how many consecutive faults must occur before the alert pin will be activated (see section 5.2.1, ?fault tolerance limits? on page 10 ). the nvft1 and nvft0 bit settings provide four different fault values as detailed in table 6-10 . both the nvft1 and nvft0 bits are factory-set to default to the logic 0 state. table 6-10. fault tolerance queue 6.4.3 nvpol bit the nonvolatile nvpol bit controls the power-up/reset default alert pin polarity. when the nvpol bit is set to the logic 0 state, the alert pin will be an active low output after the device powers up or resets. conversely, when the nvpol bit is set to the logic 1 state, the alert pin will be an active high output. the nvpol bit is set from the factory to default to the logic 0 state. 6.4.4 nvcmp/int bit the nonvolatile nvcmp/int bit controls whether the device will operate in the comparator mode or the interrupt mode after a power-up or reset sequence. setting the nvcmp/int bit to the logic 0 state (the factory default setting) will allow the device to power-up/reset in the comparator mode. alternatively, when the nvcmp/int bit is set to the logic 1 state, the device will power-up/reset in the interrupt mode. 6.4.5 nvsd bit the nonvolatile nvsd bit is used to enable the device to power-up/reset in the shutdown mode. when the nvsd bit is in the logic 0 state, the device will power-up/reset in the normal operational mode and perform continuous temperature measurements and conversions. when the nvsd bit is set to the logic 1 state, the device will automatically enter the shutdown mode after a power-up or reset sequence (see section 5.3, ?shutdown mode? on page 13 for more details). the nvsd bit is factory-set to the logic 0 state. 6.4.6 rlckdwn the one-time programmable rlckdwn bit controls whether or not both the volatile and nonvolatile versions of the configuration and limit registers will be permanently locked down. once the rlckdwn bit is set to the logic 1 state, the configuration register, t low limit register, t high limit register, nonvolatile configuration register, nonvolatile t low limit register, and nonvolatile t high limit register will be locked down and can never be modified again. since the rlckdwn bit is one-time programmable, once the bit is set to the logic 1 state, it cannot be reset again. the rlckdwn bit takes priority over the rlck bit (see section 7., ?register locking? on page 30 for more details) and is factory-set to the logic 0 state. nvft1 nvft0 consecutive faults required 0 0 1 0 1 2 1 0 4 1 1 6
25 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 6.4.7 rlck the nonvolatile rlck bit controls the reversible locking of both the volatile and nonvolatile configuration and limit registers. when the rlck bit is set to the logic 0 state, the configuration register, t low limit register, t high limit register, nonvolatile configuration register, nonvolatile t low limit register, and nonvolatile t high limit register will be unlocked and can be modified. alternatively, when the rlck bit is set to the logic 1 state, the volatile and nonvolatile configuration and limit registers will be locked and cannot be modified. when the registers are locked, only the rlck bit of the nonvolatile configuration register can be altered and reset back to a logic 0. any attempts at changing other bits in the nonvolatile configuration register will be ignored. the rlck bit is set from the factory to default to the logic 0 state. see section 7., ?register locking? on page 30 for more details. figure 6-6. write to nonvolatile configuration register figure 6-7. read from nonvolatile configuration register note: assumes the pointer register was previously set to point to the nonvolatile configuration register. scl sda start by master ack from slave ack from slave address byte nonvolatile configuration register upper byte nonvolatile configuration register lower byte pointer register byte msb msb ack from slave ack from slave stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 0 0 0 0 0 1 0 0 0 1 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 0 scl sda start by master ack from slave nack from master stop by master ack from master address byte nonvolatile configuration register upper byte nonvolatile configuration register lower byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 1 0 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 1 msb msb msb
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 26 6.5 t low and t high limit registers the 16-bit t low and t high limit registers store the user-programmable lower and upper temperature limits for the temperature alarm. like the temperature register, the temperature data values of the t low and t high limit registers are stored in the twos complement format with the msb (bit 15) of the registers containing the sign bit (zero indicates a positive number and a one indicates a negative number). as with the temperature register, the resolution selected by the r1 and r0 bits of the configuration register will determine how many bits of the t low and t high limit registers will be used; therefore, when writing to the t low and t high limit registers, up to 12 bits of data will be recognized by the device with the remaining lsbs being internally fixed to the logic 0 state. similarly, when reading from the registers, up to 12 bits of data will be output from the device with the remaining lsbs fixed in the logic 0 state. table 6-11. t low limit register and t high limit register format note: td = temperature data to set the value of either the t low or t high limit register, the master must first initiate a start condition followed by the AT30TS750A device address byte (1001aaa0 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the AT30TS750A has received the proper address byte, the device will send an ack to the master. the master must then send the appropriate pointer register byte of 02h to select the t low limit register or 03h to select the t high limit register. after the pointer register byte has been sent, the AT30TS750A will send another ack to the master. after receiving the ack from the AT30TS750A, the master must then send two data bytes to the AT30TS750A to set the value of the t low or t high limit register. any subsequent bytes sent to the AT30TS750A will simply be ignored by the device. if the master does not send two complete bytes of data prior to issuing a stop or repeated start condition, then the AT30TS750A will ignore the data and the contents of the register will not be changed. in addition to the master not sending two complete bytes of data, writing to the t low or t high limit register will be ignored and no operation will be performed under the following conditions: the nonvolatile registers are busy because of a copy operation (the nvrbsy bit of the configuration register is in the logic 1 state), the volatile and nonvolatile registers are currently locked (the rlck bit of the nonvolatile configuration register is in the logic 1 state), or the volatile and nonvolatile registers are permanently locked down (the rlckdwn bit of the nonvolatile configuration register is in the logic 1 state). however, the device will still respond with an ack, except in the case of the nonvolatile registers being busy, to indicate that it received the proper data bytes even though the contents of the t low or t high limit register will not be changed. in the case of the nonvolatile registers being busy, the device will respond with an ack to the address and pointer bytes but will then nack when the data bytes are sent from the master. in order to read the t low or t high limit register, the pointer register must be set or have been previously set to 02h to select the t low limit register or 03h to select the t high limit register (if the previous operation was a write to one of the registers, then the pointer register will already be set for that particular limit register). if the pointer register has alrea dy been set appropriately, the t low or t high limit register can be read by having the master first initiate a start condition followed by the AT30TS750A device address byte (1001aaa1 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the AT30TS750A has received the proper address byte, the device will send an ack to the master. the master can then read the upper byte of the t low or t high limit register. after the upper byte of the register has been clocked out of the AT30TS750A, the master must send an ack to indicate that it is ready for the lower byte of data. the AT30TS750A will then clock out the lower byte of the register, after which the master must send a nack to end the resolution upper byte lower byte bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12 bits sign td td td td td td td td td td td 0 0 0 0 11 bits sign td td td td td td td td td td 0 0 0 0 0 10 bits sign td td td td td td td td td 0 0 0 0 0 0 9 bits sign td td td td td td td td 0 0 0 0 0 0 0
27 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 operation. when the AT30TS750A receives the nack, it will release the sda line so that the master can send a stop or repeated start condition. if the master does not send a nack but instead sends an ack after the lower byte of the register has been clocked out, then the device will repeat the sequence by outputting the data again starting with the upper byte of the register. after the device powers up or resets, both the t low and t high limit register values will be copied from the nonvolatile t low and t high limit registers; therefore, the t low and t high limit register values will default to whatever value was previously stored in the nonvolatile t low and t high limit registers prior to power-down or reset. the value of the high temperature limit stored in the t high limit register must be greater than the value of the low temperature limit stored in the t low limit register in order for the alert function to work properly; otherwise, the alert pin will output erroneous results and will falsely signal temperature alarms. in addition, changing either value of the t high or t low limit register will cause the internal fault counter to reset back to zero. figure 6-8. write to t low or t high limit register figure 6-9. read from t low or t high limit register note: assumes the pointer register was previously set to point to the t low or t high limit register. sck sda start by master ack from slave ack from slave address byte t low or t high limit register upper byte t low or t high limit register lower byte pointer register byte msb msb ack from slave ack from slave stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 0 0 0 0 0 0 0 0 p1 p0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 0 sck sda start by master ack from slave nack from master stop by master ack from master address byte t low or t high limit register upper byte t low or t high limit register lower byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 1 0 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 1 msb msb msb
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 28 6.6 nonvolatile t low and t high limit registers the 16-bit nonvolatile t low and t high limit registers store the power-up/reset default values for the volatile versions of the t low and t high limit registers. like their volatile counterparts, the temperature data values of the nonvolatile t low and t high limit registers are stored in the twos complement format with the msb (bit 15) of the registers containing the sign bit (zero indicates a positive number and a one indicates a negative number). the values stored in both the nonvolatile t low and t high limit registers will be retained even after the device has been powered down or reset. on every power-up or reset sequence, the contents of the nonvolatile t low limit register will be copied into the t low limit register, and the contents of the nonvolatile t high limit register will be copied into the t high limit register. all temperature limit comparisons for the temperature alarm will be done using the volatile versions of the t low and t high limit registers. by utilizing the nonvolatile t low and t high limit registers, the device can power-up or reset with pre-defined temperature limits specific to the particular application; therefore, unlike standard lm75-type temperature sensors, there is no need to update the lower and upper temperature limit values after every power-up or reset. like the nonvolatile configuration register, the nonvolatile t low and t high limit registers utilize nonvolatile storage cells, so the same care must be taken when updating the registers to accommodate for the associated program time and finite program endurance limit. power must not be removed from the device during the internally self-timed programming cycle of the registers. if power is removed prior to the completion of the programming cycle, then the contents of the register being updated cannot be guaranteed. in addition, the contents of the register may become corrupt if it is programmed more than the maximum allowed number of writes. as with the temperature register, the resolution selected by the r1 and r0 bits of the configuration register will determine how many bits of the t low and t high limit registers will be used; therefore, when writing to the t low and t high limit registers, up to 12 bits of data will be recognized by the device with the remaining lsbs being internally fixed to the logic 0 state. similarly, when reading from the t low and t high limit registers, up to 12 bits of data will be output from the device with the remaining lsbs fixed in the logic 0 state. table 6-12. nonvolatile t low limit register and t high limit register format note: td = temperature data to set the value of either the nonvolatile t low or t high limit register, the master must first initiate a start condition followed by the AT30TS750A device address byte (1001aaa0 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the AT30TS750A has received the proper address byte, the device will send an ack to the master. the master must then send the appropriate pointer register byte of 12h to select the nonvolatile t low limit register or 13h to select the nonvolatile t high limit register. after the pointer register byte has been sent, the AT30TS750A will send another ack to the master. after receiving the ack from the AT30TS750A, the master must then send two data bytes to the AT30TS750A to set the value of the nonvolatile t low or t high limit register. any subsequent bytes sent to the AT30TS750A will simply be ignored by the device. if the master does not send two complete bytes of data prior to issuing a stop or repeated start condition, then the AT30TS750A will ignore the data and the contents of the register will not be changed. resolution upper byte lower byte bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 12 bits sign td td td td td td td td td td td 0 0 0 0 11 bits sign td td td td td td td td td td 0 0 0 0 0 10 bits sign td td td td td td td td td 0 0 0 0 0 0 9 bits sign td td td td td td td td 0 0 0 0 0 0 0
29 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 after the master has issued a stop or repeated start condition, the AT30TS750A will begin the internally self-timed program operation, and the contents of the nonvolatile t low or t high limit register will be updated within a time of t prog . during this time, the nvrbsy bit of the configuration register will indicate that the device is busy. if the master issues a repeated start condition instead of a stop condition, the AT30TS750A will abort the operation and the contents of the nonvolatile t low or t high limit register will not be changed. in addition to the master not sending two complete bytes of data, writing to the nonvolatile t low or t high limit register will be ignored and no operation will be performed under the following conditions: the nonvolatile registers are already busy (the nvrbsy bit of the configuration register is in the logic 1 state), the volatile and nonvolatile registers are currently locked (the rlck bit of the nonvolatile configuration register is in the logic 1 state), or the volatile and nonvolatile registers are permanently locked down (the rlckdwn bit of the nonvolatile configuration register is in the logic 1 state). however, the device will still respond with an ack, except in the case of the nonvolatile registers being busy, to indicate that it received the proper data bytes even though the program operation will not be performed. in the case of the nonvolatile registers being busy, the device will respond with an ack to the address and pointer bytes but will then nack when the data bytes are sent from the master. in order to read the nonvolatile t low or t high limit register, the pointer register must be set or have been previously set to 12h to select the nonvolatile t low limit register or 13h to select the nonvolatile t high limit register (if the previous operation was a write to one of the registers, then the pointer register will already be set for that particular limit register). if the pointer register has already been set appropriately, the nonvolatile t low or t high limit register can be read by having the master first initiate a start condition followed by the AT30TS750A device address byte (1001aaa1 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the AT30TS750A has received the proper address byte, the device will send an ack to the master. the master can then read the upper byte of the nonvolatile t low or t high limit register. after the upper byte of the register has been clocked out of the AT30TS750A, the master must send an ack to indicate that it is ready for the lower byte of data. the AT30TS750A will then clock out the lower byte of the register, after which the master must send a nack to end the operation. when the AT30TS750A receives the nack, it will release the sda line so that the master can send a stop or repeated start condition. if the master does not send a nack but instead sends an ack after the lower byte of the register has been clocked out, then the invalid device will be output by the device. the nonvolatile t low limit register is factory-set to default to 4b00h (+75 ? c) and the nonvolatile t high limit register is set to default to 5000h (+80 ? c); therefore, both registers will need to be modified if these default temperature limits are not satisfactory for the application. figure 6-10. write to nonvolatile t low or t high limit register scl sda start by master ack from slave ack from slave address byte nonvolatile t low or t high limit register upper byte nonvolatile t low or t high limit register lower byte pointer register byte msb msb ack from slave ack from slave stop by master msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 0 0 0 0 0 1 0 0 p1 p0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 0
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 30 figure 6-11. read to nonvolatile t low or t high limit register note: assumes the pointer register was previously set to point to the nonvolatile t low or t high limit register. 7. register locking all volatile and nonvolatile configuration and limit registers (the configuration register, t low limit register, t high limit register, nonvolatile configuration register, nonvolatile t low limit register, and nonvolatile t high limit register) can be locked from data changes by utilizing the rlck bit in the nonvolatile configuration register. this provides the ability to lock the registers and protect them from inadvertent or erroneous data changes, giving system designers a more robust and secure temperature sensing solution compared to other industry devices. the rlck bit can be reset so that the various registers can be modified if needed. resetting of the rlck bit is done by writing to the nonvolatile configuration register and changing the rlck bit back to a logic 0 state. when the registers are locked, only the rlck bit of the nonvolatile configuration register can be altered, and any attempts at changing other bits in the nonvolatile configuration register will be ignored. in addition, the volatile and nonvolatile configuration and limit registers can be permanently locked down by using the rlckdwn bit in the nonvolatile configuration register. when the rlckdwn bit is set, the volatile and nonvolatile configuration and limit registers will be permanently locked down so that they can never be modified again. unlike the rlck bit, the rlckdwn bit is one-time programmable and cannot be reset; therefore, the lockdown mechanism is not reversible. the rlckdwn bit takes priority over the rlck bit (see table 7-1 ). having the ability to permanently lock down the volatile and nonvolatile configuration and limit registers provides the ability to have a pre-defined, secure, and unchangeable temperature sensing solution for applications dealing with liability, risk, or safety concerns. the register locking is not affected by power cycles or reset operations, including the general call reset; therefore, if a device is power cycled or reset with the registers in the locked or locked-down state, then the registers will remain locked or locked-down when normal device operation resumes. table 7-1. register locking scl sda start by master ack from slave nack from master stop by master ack from master address byte nonvolatile t low or t high limit register upper byte nonvolatile t low or t high limit register lower byte 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 1 0 d15 d14 d13 d12 d11 d10 d9 d8 0 d7 d6 d5 d4 d3 d2 d1 d0 1 msb msb msb rlckdwn rlck locking status 0 0 volatile and nonvolatile configuration and limit registers are unlocked and can be modified. 0 1 volatile and nonvolatile configuration and limit registers are locked and cannot be modified except for the rlck bit of the nonvolatile configuration register which can be reset. 1 0 volatile and nonvolatile configuration and limit registers are permanently locked down and can never be modified again. 1 1 volatile and nonvolatile configuration and limit registers are permanently locked down and can never be modified again.
31 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 8. operations allowed during nonvolatile busy status while the AT30TS750A is busy performing nonvolatile operations such as programming the nonvolatile configuration register, certain other operations can still be executed. table 8-1 details which commands are allowed or not allowed during a nonvolatile busy operation. for those commands that are not allowed during a nonvolatile busy operation, the device will respond with a nack where it would normally respond with an ack. example: if attempting to write to the nonvolatile configuration register, the device would respond with an ack after the device address byte and pointer register byte but then respond with a nack instead of an ack after the master has sent the upper byte of configuration register data. when attempting to read a register during a nonvolatile busy operation, the device will nack instead of ack after the AT30TS750A device address byte has been received. table 8-1. commands allowed during nonvolatile busy operations note: 1. not allowed during copy nonvolatile registers to volatile registers operation. command allowed or not allowed write to pointer register allowed read temperature register allowed read configuration register allowed (1) write configuration register not allowed read t low or t high limit register allowed (1) write t low or t high limit register not allowed read or write nonvolatile configuration register not allowed read or write nonvolatile t low or t high limit register not allowed copy nonvolatile registers to volatile registers not allowed copy volatile registers to nonvolatile registers not allowed smbus alert response address (ara) not allowed general call (04h) not allowed general call reset (06h) not allowed
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 32 9. other commands the AT30TS750A incorporates additional commands for other device functions. the command opcode consists of a single byte of data that is sent from the master to the AT30TS750A in place of the pointer register byte; therefore, the device must first be addressed by the master and then given the subsequent command opcode. sending any of the command opcodes to the AT30TS750A will not change the contents of the pointer register byte. table 9-1. command listing figure 9-1. command loading 9.1 copy nonvolatile registers to volatile registers the copy nonvolatile registers to volatile registers command allows the contents of the nonvolatile configuration register, nonvolatile t low limit register, and nonvolatile t high limit register to be copied into the configuration register, t low limit register, and t high limit register. the copy process is automatically performed upon power-up or reset, but the copy nonvolatile registers to volatile registers command provides the ability to re-copy the data registers if needed. to copy the contents of the nonvolatile data registers into the volatile data registers, the master must first initiate a start condition followed by the AT30TS750A device address byte (1001aaa0 where ?aaa? corresponds to the hard- wired a 2-0 address pins). after the AT30TS750A has received the proper address byte, the device will send an ack to the master. the master must then send the command byte of b8h for the copy nonvolatile registers to volatile registers operation. after the command byte of b8h has been sent, the AT30TS750A will send another ack to the master. after the master has subsequently issued a stop or repeated start condition, the AT30TS750A will begin the internally self-timed copy operation. the copy process will take place in a maximum time of t copyr during which time the nvrbsy bit in the configuration register will indicate that the nonvolatile registers are busy. if the master issues a repeated start condition instead of a stop condition, the AT30TS750A will abort the copy operation and the contents of the volatile data registers will not be changed. the copy nonvolatile registers to volatile registers command will be ignored and no operation will be performed under the following conditions: the nonvolatile registers are already busy (the nvrbsy bit of the configuration register is in the logic 1 state), the volatile and nonvolatile registers are currently locked (the rlck bit of the nonvolatile configuration register is in the logic 1 state), or the volatile and nonvolatile registers are permanently locked down (the rlckdwn bit of the nonvolatile configuration register is in the logic 1 state). however, the device will still respond with an ack to indicate that it received the command byte even though the copy process will not be performed. command opcode copy nonvolatile registers to volatile registers b8h 1011 1000 copy volatile registers to nonvolatile registers 48h 0100 1000 scl sda start by master ack from slave ack from slave address byte command byte msb msb 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 0 0 1 a a a 0 0 c7 c6 c5 c4 c3 c2 c1 c0 0
33 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 figure 9-2. copy nonvolatile registers to volatile registers 9.2 copy volatile registers to nonvolatile registers the copy volatile registers to nonvolatile registers command allows the contents of the configuration register, t low limit register, and t high limit register to be copied into the nonvolatile configuration register, nonvolatile t low limit register, and nonvolatile t high limit register. the copy volatile registers to nonvolatile registers command can be used in the event that the volatile data registers are modified and it is desired for that newly modified data to become the new power-up/reset defaults. to copy the contents of the volatile data registers into the nonvolatile data registers, the master must first initiate a start condition followed by the AT30TS750A device address byte (1001aaa0 where ?aaa? corresponds to the hard-wired a 2-0 address pins). after the AT30TS750A has received the proper address byte, the device will send an ack to the master. the master must then send the command byte of 48h for the copy volatile registers to nonvolatile registers operation. after the command byte of 48h has been sent, the AT30TS750A will send another ack to the master. after the master has subsequently issued a stop or repeated start condition, the AT30TS750A will begin the internally self-timed copy operation. the copy process will take place in a maximum time of tcopyw during which time the nvrbsy bit in the configuration register will indicate that the nonvolatile registers are busy. if the master issues a repeated start condition instead of a stop condition, the AT30TS750A will abort the copy operation and the contents of the nonvolatile data registers will not be changed. the copy volatile registers to nonvolatile registers command will be ignored and no operation will be performed under the following conditions: the nonvolatile registers are already busy (the nvrbsy bit of the configuration register is in the logic 1 state), the volatile and nonvolatile registers are currently locked (the rlck bit of the nonvolatile configuration register is in the logic 1 state), or the volatile and nonvolatile registers are permanently locked down (the rlckdwn bit of the nonvolatile configuration register is in the logic 1 state). however, the device will still respond with an ack to indicate that it received the command byte even though the copy process will not be performed. care must be taken when copying the volatile data registers to the nonvolatile data registers in order to accommodate the associated program time and finite program endurance limit. power must not be removed from the device during the internally self-timed copy/program cycle. if power is removed prior to the completion of the copy/program cycle, then the contents of the nonvolatile registers cannot be guaranteed. in addition, the contents of the nonvolatile registers may become corrupt if programmed more than the maximum allowed number of writes. figure 9-3. copy volatile registers to nonvolatile registers scl sda address byte command byte start by master ack from slave ack from slave stop by master msb msb 1 0 0 1 a a a 0 0 1 0 1 1 1 0 0 0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 scl sda address byte command byte start by master ack from slave ack from slave stop by master msb msb 1 0 0 1 a a a 0 0 0 1 0 0 1 0 0 0 0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 34 10. smbus features and i 2 c general call 10.1 smbus alert the AT30TS750A utilizes the alert pin to support the smbus alert function when the alarm thermostat mode is set to the interrupt mode (the cmp/int bit of the configuration register is set to one) and the alert pin polarity is set to active low (the pol bit of the configuration register is set to zero). the AT30TS750A is a slave-only device, and normally, slave devices on the smbus cannot signal to the master that they want to communicate; however, the AT30TS750A uses the smbus alert function (the alert pin) to signal to the master that it wants to communicate. several smbus alert pins from different slave devices can be connected to a common smbus alert input on the master. when the smbus alert input on the master is pulled low by one of the slave devices, the master can perform a specialized read operation from the slave devices to determine which device sent the smbus alert signal. the specialized read operation is known as an smbus alert response address (ara) and requires that the master first initiate a start condition followed by the smbus ara code of 00011001. the slave device that generated the smbus alert signal will respond to the master with an ack. after sending the ack, the slave device will then output its own device address (1001aaa for the AT30TS750A where ?aaa? corresponds to the hard-wired a 2-0 address pins) on the bus. since the device address is seven bits long, the remaining eighth bit (the lsb) is used as an indicator to notify the master which temperature limit caused the alarm (the lsb will be a logic 1 if the t high limit was met or exceeded, and the lsb will be a logic 0 if the t low limit was exceeded). the smbus ara can activate several slave devices at the same time; therefore, if more than one slave responds, standard smbus arbitration rules apply and the device with the lowest address wins the arbitration. the device winning the arbitration will clear its smbus alert output after it has responded to the smbus ara and provided its device address. all other devices with higher addresses do not generate an ack and continue to hold their smbus alert outputs low until cleared. the master will continue to issue smbus ara sequences until all slave devices that generated an smbus alert signal have responded and cleared their smbus alert outputs. figure 10-1. smbus alert note: the limit bit (the lsb) of the device address byte will be ?1? or ?0? depending on if the t high or t low limit was exceeded. sck sda smbus ara code AT30TS750A device address byte start by master ack from slave nack from master stop by master msb msb 0 0 0 1 1 0 0 1 0 1 0 0 1 a2 a1 a0 limit 1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9
35 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 10.2 smbus timeout the AT30TS750A supports the smbus timeout feature in which the AT30TS750A will reset its serial interface and release the smbus (stop driving the bus and let sda float high) if the scl pin is held low for more than the minimum t timeout specification. the AT30TS750A will be ready to accept a new start condition before t timeout maximum has elapsed. figure 10-2. smbus timeout 10.3 general call the AT30TS750A will respond to an i 2 c general call address (0000000) from the master only if the eighth bit (the lsb) of the general call address byte is zero. if the general call address byte is 00000000, then the device will send an ack to the master and await a command byte from the master. if the master sends a command byte of 04h, then the AT30TS750A will re-latch the status of its address pins in case the system has assigned a new address to the device. if the master sends a command byte of 06h (general call reset), then the AT30TS750A will re-latch the status of its address pins and perform a reset sequence. the reset sequence will cause the contents of the nonvolatile data registers to be copied into the volatile data registers, and the device will be busy for a maximum time of t por during the reset and copying operation. device will release bus and be ready to accept a new start condition within this time t timeout (max) t timeout (min) scl
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 36 11. electrical specifications 11.1 absolute maximum ratings* 11.2 dc and ac operating range notes: 1. device operation is guaranteed from -40 c to +125 c. 2. device operation is not guaranteed at -55 c but ensured by characterization. temperature under bias . . . . . . . -40c to +125c storage temperature . . . . . . . . . -65c to +150c supply voltage with respect to ground . . . . . . . . . . . -0.5v to +7.0v alert pin . . . . . . . . . . . . . . . -0.5v to v cc + 0.3v all input voltages with respect to ground . . . . . . . -0.5v to v cc + 0.5v all other output voltages with respect to ground . . . . . . . -0.5v to v cc + 0.5v *notice: stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. functional operation of the device at these ratings or any other conditions beyond those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage extremes referenced in the ?absolute maximum ratings? are intended to accommodate short duration undershoot/overshoot conditions and does not imply or guarantee functional device operation at these levels for any extended period of time. pull-up voltages applied to the alert pin that exceed the ?absolute maximum ratings? may forward bias to the esd protection circuitry. doing so may result in improper device function and may corrupt temperature measurements. AT30TS750A operating temperature (case) industrial high temperature -55 ? c to +125 ? c (1)(2) v cc power supply 1.7v to 5.5v
37 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 11.3 dc characteristics note: 1. typical values characterized at t a = +25c at v cc = 1.8v, 3.0v, and 5.0v unless otherwise noted. symbol parameter v cc range condition min typ (1) max units i cc1 active current, bus inactive 1.7v v cc 2.0v active temperature conversions 60 75 a 2.7v v cc 3.6v 65 95 4.5v v cc 5.5v 85 125 i cc2 active current, bus active 1.7v v cc 2.0v active temperature conversions, f scl = 400khz 120 160 a 2.7v v cc 3.6v 150 225 4.5v v cc 5.5v 225 325 i cc3 active current, nonvolatile register read 1.7v v cc 2.0v active temperature conversions, f scl = 400khz 0.15 0.20 ma 2.7v v cc 3.6v 0.23 0.35 4.5v v cc 5.5v 0.48 0.63 i cc4 active current, nonvolatile register copy 1.7v v cc 2.0v active temperature conversions, f scl = 400khz 0.70 1.50 ma 2.7v v cc 3.6v 2.00 3.40 4.5v v cc 5.5v 2.50 4.40 i sd1 shutdown mode current, bus inactive 1.7v v cc 2.0v 0.4 2.5 a 2.7v v cc 3.6v 0.6 3.5 4.5v v cc 5.5v 1.2 5.5 i sd2 shutdown mode current, bus active 1.7v v cc 2.0v f scl = 400khz 110 140 a 2.7v v cc 3.6v 130 180 4.5v v cc 5.5v 180 270 i li input leakage current v in = cmos levels 1 a i lo output leakage current v out = cmos levels 1 a v il input low voltage 0.3 x v cc v v ih input high voltage 0.7 x v cc v v ol1 output low voltage i ol = 3ma 0.4 v v ol2 output low voltage, alert pin i ol = 4ma 0.4 v v oh output high voltage i oh = -100 a v cc - 0.2 v
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 38 11.4 temperature sensor accuracy and conversion characteristics notes: 1. typical values characterized at v cc = 3.3v, t a = +25c unless otherwise noted. 2. sensor accuracy characterized to this range but not tested or guaranteed. 11.5 ac characteristics symbol parameter condition min typ (1) max units t acc sensor accuracy t a = 0c to +85c 0.5 1.0 ? c t a = -25c to +105c 1.0 2.0 t a = -40c to +125c 2.0 3.0 t a = -55c to +125c (2) 3.0 t res conversion resolution selectable 9 to 12 bits 0.5 (9 bits) 0.0625 (12 bits) ? c t conv conversion time 9-bit resolution 25 37.5 ms 10-bit resolution 50 75 11-bit resolution 100 150 12-bit resolution 200 300 symbol parameter fast mode plus units min max f scl serial clock frequency 1 (1) 1000 khz t sclh clock high time 260 ns t scll clock low time 500 ns t r clock/data input rise time 120 ns t f clock/data input fall time 120 ns t sudat data in setup time 50 ns t hddat data in hold time 0 ns t v output valid time 350 ns t oh output hold time 0 ns t buf bus free time between stop and start condition 500 ns t susta repeated start condition setup time (scl high to sda low) 50 ns t hdsta start condition hold time (sda low to scl low) 50 ns t susto stop condition setup time (scl high to sda high) 50 ns t ns noise suppression input filter time 50 ns t timeout smbus timeout time 25 75 ms c load capacitive load for scl and sda lines 400 pf
39 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 note: 1. minimum clock frequency must be at least 1khz to avoid activating the smbus timeout feature. figure 11-1. smbus/i 2 c timing diagram 11.6 nonvolatile register characteristics note: 1. typical values characterized at v cc = 3.3v, t a = +25c unless otherwise noted. 11.7 power-up conditions figure 11-2. power-up timing scl sda start condition stop condition repeated start condition start condition t sckh t sckh t sudat t sckl t hddat t oh t r t f t susto t v t buf t hdsta t susta in in out out in in symbol parameter min typ (1) max units t prog nonvolatile register program time 1.0 5.0 ms t copyw volatile to nonvolatile register copy time 1.0 5.0 ms t copyr nonvolatile to volatile register copy time 100 200 s n endur nonvolatile register program/copy endurance 50,000 100,000 cycles symbol parameter min max units t por power-on reset time 1 ms v por power-on reset voltage range 1.6 v t pu v cc v cc (min) v por (max) v por (min) time do not attempt device access during this time device access permitted t por
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 40 11.8 pin capacitance note: 1. not 100% tested (value guaranteed by design and characterization). 11.9 input test waveforms and measurement levels 11.10 output test load symbol parameter min max units c i/o (1) input/output capacitance (sda and alert pins) v i/o = 0v 8 pf c in (1) input capacitance (a 2-0 and scl pins) v in = 0v 6 pf ac input levels ac measurement level t r , t f < 5ns (10% to 90%) 0.9v cc 0.1v cc v cc 2 device under te s t 100pf
41 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 12. ordering information 12.1 atmel ordering code detail 12.2 green package options (pb/halide-free/rohs compliant) note: the shipping carrier option code is not marked on the devices. AT30TS750A-ss8m-b atmel designator product family device type device revision 30ts = digital temperature sensor eeprom 0 = nonvolatile registers shipping carrier option device grade package option b = bulk (tubes) y = bulk (trays) t = tape and reel voltage option m = 1.7v to 5.5v 8 = green, nipdau lead finish, industrial high temperature range (?40c to +125c) accuracy guaranteed ss = 8-lead, 0.150" wide soic xm = 8-lead, 3.0mm x 3.00mm msop ma = 8-pad, 2.00mm x 3.00mm x 0.6mm atmel ordering code package lead (pad) finish operating voltage max. freq. (khz) operation range AT30TS750A-ss8m-b 8s1 nipdau 1.7v to 5.5v 1000 industrial high temperature (-55c to +125c) AT30TS750A-ss8m-t AT30TS750A-xm8m-b 8xm AT30TS750A-xm8m-t AT30TS750A-ma8m-t 8ma2 package type 8s1 8-lead, 0.15? wide, plastic gull wing small outline (jedec soic) 8xm 8-lead, 3.00mm x 3.00mm, plastic miniature small outline (msop) 8ma2 8-pad, 2.00mm x 3.00mm x 0.60mm, thermally enhanced plastic ultra thin dual flat no lead (udfn)
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 42 13. part marking detail drawing no. rev. title 30tsx75xasm a 10/16/12 at30tsx70xasm , AT30TS750A, at30tse752a, at30tse754a & at30tse758a standard marking information for package offering package mark contact: dl-cso-assy_eng@atmel.com aaaaaaaa ###m @ atml8yww 8-lead soic 8-lead udfn ### 8m@ yxx 2.0 x 3.0 mm body note 2: package drawings are not to scale note 1: designates pin 1 AT30TS750A, at30tse752a, at30tse754a & at30tse758a: package marking information catalog number truncation AT30TS750A truncation code ###: t4a at30tse752a truncation code ###: t5a at30tse754a truncation code ###: t6a at30tse758a truncation code ###: t7a date codes voltages y = year m = month ww = work week of assembly % = minimum voltage 2: 2012 6: 2016 a: january 02: week 2 m: 1.7v min 3: 2013 7: 2017 b: february 04: week 4 4: 2014 8: 2018 ... ... 5: 2015 9: 2019 l: december 52: week 52 country of assembly lot number grade/lead finish material @ = country of assembly aaa...a = atmel wafer lot number 8: industrial (c) (-40c to 125c)/nipdau trace code atmel truncation xx = trace code (atmel lot numbers correspond to code) at: atmel example: aa, ab.... yz, zz atm: atmel atml: atmel yww@ 8m xx ### 8-lead msop
43 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 14. packaging information 14.1 8s1 ? 8-lead jedec soic drawing no. rev. title gpc common dimensions (unit of measure = mm) symbol min nom max note a1 0.10 ? 0.25 a 1.35 ? 1.75 b 0.31 ? 0.51 c 0.17 ? 0.25 d 4.80 ? 5.05 e1 3.81 ? 3.99 e 5.79 ? 6.20 e 1.27 bsc l 0.40 ? 1.27 ? ? 0 ? 8 ? e 1 n top view c e1 end view a b l a1 e d side view package drawing contact: packagedrawings@atmel.com 8s1 g 6/22/11 notes: this drawing is for general information only. refer to jedec drawing ms-012, variation aa for proper dimensions, tolerances, datums, etc. 8s1, 8-lead (0.150? wide body), plastic gull wing small outline (jedec soic) swb
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 44 14.2 8xm ? 8-lead msop title drawing no. gpc rev. package drawing contact: packagedrawings@atmel.com 8xm tzd a 8xm, 8-lead, 3.0x3.0mm body, plastic thin shrink small outline package (tssop/msop) 3/1/11 common dimensions (unit of measure = mm) symbol min nom max note a - - 1.10 a 1 0.05 0.10 0.15 a 2 0.75 0.85 0.95 b 0.22 - 0.38 d 2.90 3.00 3.10 1 e 4.90 bsc e 1 2.90 3.00 3.10 1 e 0.65 bsc l 0.40 0.55 0.80 2 a e o c c a 1 n pin 1 e 1 1 a 2 3 side view end view detail 'a' top view seating plane 1 2 3 see detail "a" 2 l 4 1. one another within 0.10mm at seating plane. 4. 3. 2. formed leads shall be planar with respect to terminal positions are shown for reference only. for soldering to a substrate. dimension is the length of terminal protrusions shall not exceed 0.15mm per side. at datum plane -h- , mold flash or flash or protrusions, and are measured dimensions "d" & "e1" do not include mold notes: c 0.10 c l bsc 0.25 d c 0.20 b a 2x (n/2 tips) e 1 0.07 r. min 2 places -c- seating plane -h- -a- -b- s 0.05 5. datums -a- and -b- to be determined by datum plane -h- . bottom view n 3 2 1 8 0 c c o 4 b
45 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 14.3 8ma2 ? 8-pad udfn drawing no. rev. title gpc 8ma2 f 6/6/14 8ma2, 8-pad 2 x 3 x 0.6mm body, thermally enhanced plastic ultra thin dual flat no-lead package (udfn) ynz common dimensions (unit of measure = mm) symbol min nom max note a 0.50 0.55 0.60 a1 0.0 0.02 0.05 a2 - - 0.55 d 1.90 2.00 2.10 d2 1.20 - 1.60 e 2.90 3.00 3.10 e2 1.20 - 1.60 b 0.18 0.25 0.30 3 c 1.52 ref l 0.30 0.35 0.40 e 0.50 bsc k 0.20 - - top view side view bottom view package drawing contact: packagedrawings@atmel.com c e pin 1 id d 8 7 6 5 1 2 3 4 a a1 a2 d2 e2 e (6x) l (8x) b (8x) pin#1 id k 1 2 3 4 8 7 6 5 notes: 1. this drawing is for general information only. refer to drawing mo-229, for proper dimensions, tolerances, datums, etc. 2. the pin #1 id is a laser-marked feature on top view. 3. dimensions b applies to metallized terminal and is measured between 0.15 mm and 0.30 mm from the terminal tip. if the terminal has the optional radius on the other end of the terminal, the dimension should not be measured in that radius area. 4. the pin #1 id on the bottom view is an orientation feature on the thermal pad.
AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 46 15. errata 15.1 no errata
47 AT30TS750A [datasheet] atmel-8855f-dts-AT30TS750A-datasheet_102014 16. revision history doc. rev. date comments 8855f 10/2014 increase the i cc1 4.5v ? v cc ? 5.5v typical from 75 to 85 and maximum from 100 to 125. update ths udfn, 8ma2 package outline drawing. 8855e 05/2014 update the dc characteristics table, power-up conditions condition table, t acc sensor accuracy parameter condition, i cc4 values, and remove v hv parameter. update 8ma2 package drawing. 8855d 09/2013 update the absolute maximum ratings table. 8855c 07/2013 update from preliminary to complete/release status. 8855b 05/2013 update disclaimer page. updated tables 11-3 and 11-7. update 8ma2 package drawing. 8855a 02/2013 initial document release.
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